1. Field of the Invention
The present invention relates to phase/frequency comparators used in phase locked loops (PLL's), and more particularly to two-input/two-output comparators, the first output providing a signal when the first input is in phase advance with respect to the second, and the second output providing a signal when the second input is in phase advance with respect to the first.
2. Discussion of the Related Art
FIG. 1 illustrates a phase/frequency comparator commonly used in charge-pump PLL's. Such a comparator and its use are described in U.S. Pat. No. 3,610,954 which is herein incorporated by reference.
Input signals f.sub.A and f.sub.B, the phases and/or frequencies of which must be compared, are in the form of rectangular signals and are applied to input terminals 10 and 12, respectively. Each input terminal is connected to a first input of a respective NAND gate 14 and 15. The output of each NAND gate 14 and 15 is connected to a first input of a respective NAND gate 17 and 18. The outputs of NAND gates 17 and 18 are looped back on a second input of the respective gate 14 and 15. The outputs of gates 17 and 18 are also connected to output terminals A and B, respectively.
The output of each gate 14 and 15 is also connected to a respective input of an NAND gate 20 and to an input of a respective NAND gate 22 and 24. Each gate 22 and 24 forms with a respective NAND gate 26 and 28, a latch. In each latch, the output of one of the first gates is looped back onto the free input of the second gate, and the output of the second gate is looped back onto a free input of the first gate. The output of each gate 22, 24 is connected to a second input of the respective gate 17 and 18 and to another respective input of gate 20. The output of gate 20 is connected to a third input of gates 17 and 18 and to the remaining inputs of gates 26 and 28.
At rest, outputs A and B are at 1 and signals f.sub.A and f.sub.B are supposed to be 1. In this case, gates 14, 15, 26 and 28 are at 0 and gates 20, 22 and 24 are at 1. If, for example, signal f.sub.A goes to 0, gate 14 goes to 1. Then, the three inputs of gate 17 are to 1 and the output A of gate 17 goes to 0. While going to 0, output A locks the state of gate 14, that is, independently of the state of signal f.sub.A, gate 14 remains to 1. The state of gate 17 (therefore of output A) can no longer be modified by signal f.sub.A. Additionally, the change of state of gate 14 has not affected whatsoever the latch circuit 22-26, the output of gate 22 remaining at 1.
When signal f.sub.B goes to 0, gate 15 goes to 1. All the inputs of gate 20 are set to 1. Then, gate 20 goes to 0 which urges outputs A and B to 1. Thus, output A has gone to 0 between a falling edge of signal f.sub.A and the next falling edge of signal f.sub.B. Theoretically, the state of output B does not vary during this interval.
On the other hand, the zero-crossing of gate 20 switches the states of storing circuits 22-26 and 24-28, which allows for constantly maintaining outputs A and B at state 1 and urging gate 20 to 1. This enables outputs A and B to maintain their state 1 independently of the instants when the rising edges of signals f.sub.A and f.sub.B occur subsequently to the falling edge of signal f.sub.A. The latch circuit 22-26 is restored to its initial state as soon as signal f.sub.A and output A are at 1. Circuit 24-28 is restored to its initial state as soon as signal f.sub.B and output B are at 1.
FIG. 2 shows exemplary waveforms of signals f.sub.A and f.sub.B and the corresponding output signals at terminals A and B. Signals f.sub.A and f.sub.B are represented such that, until a time t.sub.4, the frequency of signal f.sub.A is higher than the frequency of signal f.sub.B , and lower than that of f.sub.B after time t.sub.4.
At times t.sub.1, t.sub.2 and t.sub.3, the falling edges of signal f.sub.A occur prior to the corresponding falling edges of signal f.sub.B. Then, as described in relation with FIG. 1 and as represented, output A crosses zero between each falling edge of signal f.sub.A and the next falling edge of signal f.sub.B.
At times t.sub.5, t.sub.6 and t.sub.7, the falling edges of signal f.sub.B occur prior to the corresponding falling edges of signal f.sub.A. Then, as represented, output B crosses zero between each falling edge of signal f.sub.B and the next falling edge of signal f.sub.A.
The above explanations have been given assuming that the various gates instantaneously switch as soon as their input signals are switched. Of course, this is not exactly the case in practice, and each gate has a given switching time. As a result, parasitic pulses occur. Particularly, when a falling edge of signal f.sub.B appears at input 12 after a falling edge at input 10, this generates, as indicated, the sequential switching of gates 15, 20 and 17 and should not affect gate 181 However, since gate 15 is connected to gate 18, the latter temporarily has all its inputs to 1 before being inhibited by the switching of gate 20. This causes a short parasitic pulse at output B lasting approximately for the switching time of gate 20.
FIG. 2 also shows the above mentioned parasitic pulses. These parasitic pulses occur at output A at each falling edge of signal f.sub.A after time t.sub.4 and occur at output B at each falling edge of signal f.sub.B before time t.sub.4.
When outputs A and B respectively control current sources for charging and discharging a capacitor, the parasitic pulses are of such short durations that they have a negligible influence upon the charge of the capacitor and may therefore be tolerated. However, in some applications, for example if a digital circuit is controlled by outputs A and B, parasitic pulses are no longer tolerable.